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| Frequency Change vs. Input Voltage: ±5ppm max. (VDD±5%) |
| Input Voltage: +1.8V±5%, +2.5V±5%, +3.3V±5% |
| Output Load TTL: 2TTL gates CMOS: 15pF |
| Rise/Fall Time TTL: 6ns max, 4ns typ. (0.4V to 2.4V) CMOS: 6ns max, 4ns typ. (20%~80% Vdd) |
| Duty Cycle: 50±10% standard, 50±5% option |
| Integrated Phase Jitter: 1ps maximum (12kHz to 20MHz) |
| Period Jitter RMS: 2.0ps typical |
| Period Jitter Peak to Peak: 14ps |
| Start-up time: 10ms max., 3ms typical |
| Current Consumption: 10 to 45mA, frequency dependant (27MHz: 10mA typical at 3.3V, 20mA typical at 5.0VDC) |
| Linearity: 6% typical, 10% maximum |
| Modulation Bandwidth: 10kHz min., measured at Vcont = 1.65V or2.5V |
| Input Impedance: 1MΩ typical |
| Slope Polarity: Monotonic and Positive, increasing control voltage increases output frequency. |
| Ageing: ±3ppm per year maximum |
| RoHS Status: RoHS Compliant and lead (Pb) free |
