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| Output Load TTL: 2 TTL gates CMOS: 15pF |
| Rise/Fall Times TTL: 6ns max., 4ns typical Measured between 0.4V to 2.4V CMOS: 6ns max., 4ns typical Measured between 20% to 80% of wave form, (CL = 15pF) |
| Duty Cycle: 50%±10% standard, 50%±5% is available, add 'S' to part number |
| Integrated Phase Jitter: 200fs max. (12kHz to 20MHz) |
| Start-up Time: 10ms max., 5ms typical |
| Current Consumption: 10~45mA, freq. dependant e.g. 27MHz: 10mA @ 3.3V 27MHz: 20mA @5.0V |
| Linearity: 6% typical, 10% max |
| Modulation Bandwidth: 10kHz min. Measured at -3dB with V control at 1.65V or 2.5V |
| Input Impedance: 1MΩ typical |
| Slope Polarity: Monotonic and positive (An increase of control voltage increases output frequency.) |
| Ageing: ±3ppm per year max. |
| Tri-state Enable high: No connection or VDD-0.5V min. is applied to Tri-state pin to enable. Disable: Ground +0.5V max. disables output. (High impedance) |
